Connection device and test system

ABSTRACT

To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure.

This application is a Continuation application of U.S. application Ser.No. 11/853,979, filed Sep. 12, 2007, which, in turn, is a ContinuationApplication of U.S. application Ser. No. 10/873,168, filed Jun. 23, 2004(now U.S. Pat. No. 7,285,430), which, in turn, is a Continuationapplication of U.S. application Ser. No. 09/971,606, filed Oct. 9, 2001(now U.S. Pat. No. 6,759,258), and which, in turn, is a Continuationapplication of U.S. application Ser. No. 09/423,385, filed Nov. 8, 1999(now U.S. Pat. No. 6,305,230), and the entire disclosures of which arehereby incorporated by reference. U.S. application Ser. No. 09/423,385,filed Nov. 8, 1999 (now U.S. Pat. No. 6,305,230) is a Section 371 ofInternational Application No. PCT/JP98/01722, filed Apr. 15, 1998.

TECHNICAL FIELD

This invention relates to a connection device and test system forsending an electrical signal to electrodes through contact terminals incontact with matching electrodes and implementing testing, such aspass/fail tests of items for inspection, such as semiconductor devices.The invention relates in particular to a connection device and testsystem to prevent harm or wear to the items under test, such assemiconductor devices having numerous pin type electrodes disposed at anarrow pitch.

BACKGROUND OF THE INVENTION

A method is known for testing electrical characteristics ofsemiconductor devices, such as VLSI devices, at the wafer level with aconventional thin-type probe card, as disclosed in the lecture archivesof the 1988 Annual International Test Conference on Membrane Probe CardTechnology, from pages 601 to 607 (hereafter Publication 1). In thisconductive test probe as described in Publication 1, wiring was formedby lithography on a flexible dielectric film, and a semi-spherical bump,formed by plating in a through-hole of dielectric film formed at aposition matching the electrodes of the semiconductor device-fortesting, was utilized as the contact terminal. In the test methoddescribed in this Publication 1, the bump, which is connected to thetesting circuit by way of the wiring substrate and wiring formed on thesurface of the dielectric film, was caused to rub against the electrodeof the semiconductor device under test to make contact by a springeffect, and testing was then implemented by an exchange of electricalsignals.

Other known methods are described Japanese Laid-Open Patent 2-163664(hereafter Publication 2), Japanese Laid-Open Patent 5-243344 (hereafterPublication 3), Japanese Laid-Open Patent 8-83824 (hereafter Publication4), Japanese Laid-Open Patent 8-220138 (hereafter Publication 5), andJapanese Laid-Open Patent 7-283280 (hereafter Publication 6).

In Publication 1 as well as Publications 2, 3, 4 and 5, a testing methodis disclosed using a probe device with an automatic offset functionhaving a conveyor means (structure with a lower conductive stage toreceive an upper conductive stage installed on a pivot) to make springcontact with a support means to basically form a joint level surfacebetween the flat membrane probe and an essentially flat device undertest.

Further, a method is disclosed in the Publications 2, 3, 4 and 5 whichproposes to install a cushioning material between the lower conductivestage and the membrane.

Also, in the Publication 5, a method is disclosed for use of amicro-strip line achieved by low-impedance and impedance matching byinstalling and grounding a metallic conductive layer on the reverse sideof a thin conductive pattern formed on a metal protuberance.

Also, in the Publication 6, a method is disclosed for use of a probingdevice wherein a contact terminal shaped with a point at the tip,obtained by etching a crystalline mold material of anisotropic shape, isconnectably embedded in a lead out wiring formed from an insulator film,and this insulator film encloses the silicon wafer forming the substrateand cushioning layer forming a single unit with respect to the wiringsubstrate.

As described in the above Publication 1, the contact point (protuberanceon the electrode) of the probe formed from a flat or semi-spherical bumpmakes a friction contact, rubbing away the oxidation on the material ofthe device under test created by a rubbing contact (scribing action)from the aluminum electrode or solder electrode of the probe contactpoint, and the oxidation is also rubbed away from the electrode materialsurface to make contact with the conductive metal material at the lowersurface. As a result, the scribing action of the electrode at thecontact point creates debris from the electrode material causingelectrical shorts between the wiring or wiring layers or creatingforeign matter. The electrode in many cases is subjected to furtherdamage and wear by the scribing (rubbing) action of the probe whichapplies a weight of several hundred mN to assure contact with theelectrode.

The methods of Publication 2 through Publication 5 have a function forallowing the contact point group to make contact in parallel with thesurface of the electrodes of the device under test; however, thisstructure applies a contact load by displacement of a plate spring sothat the spring plate is greatly displaced in terms of a uniform load,making application of a load of several hundred mN per pin necessarywhen making contact—Consequently, this load creates the problem ofdamage and wear on the electrodes of the device under test as well as onthe active device and wiring directly beneath those electrodes andrelated problems occurring due to this damage and wear.

In the method of Publication 6, a problem occurs in that absorbingheight differences in the contact terminal and electrodes of the deviceunder test, or absorbing the impact received by the contact terminalsfrom driving the material mount holding the device under test duringprobing, just by means of the cushioning layer is difficult and may alsocreate possible wear and tear on the device under test such as asemiconductor device.

Therefore, none of the known techniques as described above, allows forlow load, stable probing of devices under test, such as semiconductorelements having many pins disposed at a narrow pitch caused by highdensity, without causing damage or wear.

SUMMARY OF THE INVENTION

This invention has the object of providing a connection device and testsystem that eliminates the problems of the prior art and is capable oflow load, stable probing of devices under test having numerous pins withA narrow pitch and high density, such as semiconductor elements, withoutcausing damage, and is further capable of sending high speed electricalsignals namely high frequency electrical signals.

This invention has the further object of providing a connection deviceand test system that applies a light load using only downward pressurefrom the pointed tip of the contact terminal onto the electrodes of thedevice under test without generating debris, such as from the electrodematerial, thereby to achieve a stable connection with low resistance.

This invention has the still further object of providing a connectiondevice and test system wherein a contact terminal having a pointed tipand the lead wiring are formed separately, and both are connected toform a contact wire with lead wiring so that the yield duringmanufacture is improved, the manufacturing time is shortened and thecost is decreased.

In order to achieve the above mentioned objects, the connection deviceof this invention for making electrical contact with array of electrodesof devices under test, such as semiconductor elements, and forperforming an exchange of electrical signals is characterized by havinga support member for supporting the connection device, a plurality ofpointed contact terminals arrayed on the probing side, a multilayer filmhaving a plurality of lead out wires electrically connected to theperiphery of the contact terminals and a ground layer enclosing aninsulation layer facing the plurality of lead out wires, a clampingmember installed on the multilayer film to eliminate slack or droopingin the applicable area and a contact pressure means such as a springprobe for making the tip of each of the contact terminals contact eachof the electrodes by applying contact pressure from the support memberto the clamping member.

Also, in order to achieve the above mentioned objects, the connectiondevice of this invention for making electrical contact with an array ofelectrodes of devices under test, such as semiconductor elements, andfor performing an exchange of electrical signals is characterized byhaving a support member for supporting the connection device, aplurality of pointed contact terminals arrayed on the probing side, amultilayer film having a plurality of lead out wires electricallyconnected to the periphery of the contact terminals and a ground layerenclosing an insulation layer facing the plurality of lead out wires, aclamping member installed on the multilayer film to eliminate slack ordrooping in the applicable area, a contact pressure means such as aspring probe for making the tip of each of the contact terminals contacteach of the electrodes by applying contact pressure from the supportmember to the clamping member, and a compliance mechanism to make thesupport member engage with the clamping member so that the tips of thecontact terminal group are arrayed in parallel with the electrode groupterminal surface, when making the tips of the contact terminals contactthe surface of the electrodes.

Further, in order to achieve the above mentioned objects, the connectiondevice of this invention for making electrical contact with an array ofelectrodes of devices under test, such as semiconductor elements, andfor performing an exchange of electrical signals is characterized byhaving a support member for supporting the connection device, aplurality of pointed contact terminals arrayed in an area on the probingside, a multilayer film having a plurality of lead out wireselectrically connected to the periphery of the contact terminals and aground layer enclosing an insulation layer facing the plurality of leadout wiring, a frame clamped so as to enclose the applicable area on theprobing side and the rear of the opposite side on the multilayer film, aclamping member to install the frame having a portion to make theapplicable area project out to eliminate slack in the multilayer film, acontact pressure means such as a spring probe for making the tip of eachof the contact terminals contact each of the electrodes by applyingcontact pressure from the support member to the clamping member, and acompliance mechanism to make the support member engage with the clampingmember so that the tips of the contact terminals are arrayed in parallelwith the electrode group terminal surface, when making the tips of thecontact terminals contact the surface of the electrodes.

Also, the connection device of this invention is characterized in that acushioning device is installed between the clamping member and the rearsides of the area of the multilayer film.

The connection device of this invention has a multilayer filmcharacterized in that the lead out wiring and the contact terminals areconnected by metal such as solder or heat expansion metal or aconductive sheet of anisotropic shape.

The connection device of this invention has a multilayer filmcharacterized in that the lead out wiring and the connective wiringformed in the contact terminals are connected by metal such as solder orheat expansion metal or a conductive sheet of anisotropic shape.

The connection device of this invention is characterized by having acircuit board mounted on the probing side of the support member, and theelectrodes formed on the circuit board are electrically connected withthe lead out wiring on the periphery of the multilayer film.

The test system of this invention is characterized by a connectiondevice having a support means for a material support system to mount andsupport the device under test, a plurality of pointed contact terminalsarrayed in an area on the probing side, a multilayer film having aplurality of lead out wires electrically connected to the contactterminals and a ground layer enclosing an insulation layer facing saidplurality of lead out wires, a clamping member installed on saidmultilayer film so as to eliminate slack in the applicable area of themultifilm layer, a contact pressure means for making the tips of thecontact terminals contact each of the electrodes by applying contactpressure from the support member to the clamping member, and furthercharacterized by having a tester electrically connected to the lead outwires connecting to the periphery of the multilayer film of theconnection device, a positioning means to align the positions of thecontact terminal group arrayed in the multilayer film of the connectiondevice and an electrode group arrayed on the device under test, and theposition aligned electrode group is made to contact the contact terminalgroup aligned by the positioning means and exchange electrical signalsbetween the tester and the device under test to perform testing.

The test system of this invention is also characterized by a connectiondevice having a support means for a material support system to mount andsupport the device under test, a plurality of pointed contact terminalsarrayed in an area on the probing side and electrically connected to thelead out wires of the multilayer film by metal such as solder or heatexpansion metal or a conductive sheet of anisotropic shape, and amultilayer film having a plurality of lead out wires electricallyconnected at the periphery to these contact terminals by way of metalsuch as solder or heat expansion metal or a conductive sheet ofanisotropic shape and having a ground layer enclosing an insulationlayer facing said plurality of lead out wires, a clamping member toinstall said multilayer film so as to eliminate slack in the applicablearea of the multilayer film, and a contact pressure means for making thetips of the contact terminals contact each of the electrodes by applyingcontact pressure from the support member to the clamping member, andfurther characterized by having a tester electrically connected to thelead out wires connecting to the periphery of the multilayer film of theconnection device, a positioning means to align the positions of thecontact terminal group arrayed in the multilayer film of the connectiondevice and an electrode group arrayed on the device under test, and theposition aligned electrode group is made to contact the contact terminalgroup aligned by the positioning means and exchange electrical signalsbetween the tester and the device under test to perform testing.

The test system of this invention is also characterized by a connectiondevice having a support means for a material support system to mount andsupport the device under test, a plurality of pointed contact terminalsarrayed in an area on the probing side and electrically connected to thelead out wiring of the multilayer film, and a multilayer film having aplurality of lead out wires electrically connected at the periphery tothese contact terminals and having a ground layer enclosing aninsulation layer facing said plurality of lead out wires, a clampingmember to install said multilayer film so as to eliminate slack in theapplicable area of the multifilm layer, and a contact pressure means formaking the tips of the contact terminals contact each of the electrodesby applying contact pressure from the support member to the clampingmember, and further characterized by having a tester electricallyconnected to the lead out wires connecting to the periphery of themultilayer film of the connection device, a positioning means to alignthe positions of the contact terminal group arrayed in the multilayerfilm of the connection device and an electrode group arrayed on thedevice under test, and the position aligned electrode group is made tocontact the contact terminal group raised to a desired height on thematerial support system by the positioning means and exchange electricalsignals between the tester and the device under test to perform testing.

Therefore, in the structure of the invention as described above, stable,low load probing of many pins disposed at a narrow pitch on asemiconductor device with a high electrode density can be performedwithout damage to the device under test, and, furthermore, a high speedexchange of electrical signals or in other words high frequencyelectrical signals (high frequencies from about 100 MHz up to some 10GHz) can be achieved.

Also, in the above described structure of this invention, the compliancemechanism achieves a parallel array of pointed contact terminals withoutslack in the applicable area of the multilayer film so that the pointedcontact terminal group makes stable contact with the electrode group ofthe device under test, and so that a downward pressure with a low loadon each pin (approximately 3 to 50 mN) achieves a stable connection witha low resistance of about 0.05 to 0.1Ω and without generating debrisfrom the electrode material, etc.

Further, in the above described structure of this invention, one or aplurality of semiconductor devices from among a plurality ofsemiconductor devices (chips) arrayed on a wafer can simultaneously bestably and reliably contacted at a small contact pressure (about 3 to 50mN per pin) on the oxidized surface of the electrodes, formed forinstance of aluminum or solder with a stable and low resistance value of0.05 to 0.1Ω, and operational tests of each semiconductor device can beperformed by the tester. In other words, the above structure of thisinvention can handle devices with a high electrode density as well as anarrow pitch, and they further can perform testing by simultaneousprobing of many discrete chips and can also perform operational testswith high speed electrical signals (high frequencies from about 100 MHzup to some 10 GHz).

Also, in the structure of this invention, forming the contact terminaland the lead out wire separately from each other and then connectingboth to form a lead out wire with the contact terminal improves theproductivity during manufacture and achieves a connection device andtest system with a shorter manufacturing time and a low price.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1( a) is a perspective view showing the wafer as the item undertest arrayed with semiconductor devices (chips).

FIG. 1( b) is an enlarged, perspective view showing one semiconductordevice (chip).

FIG. 2 is a cross sectional view showing an essential portion of thefirst embodiment of the connection device of this invention.

FIG. 3 is a cross sectional view showing the pointed contact terminalsarrayed in the multilayer film in contact with the electrode surfaces ofthe device under test in the first embodiment of the connection deviceshown in FIG. 2.

FIG. 4 is a cross sectional view showing a portion of the multilayerfilm with the insulator layer enclosed from opposite directions by thelead out wire and ground layer.

FIG. 5 is a cross sectional view showing an essential portion of thesecond embodiment of the connection device of this invention.

FIG. 6 is a cross sectional view showing an essential portion of thethird embodiment of the connection device of this invention.

FIG. 7 is a cross sectional view showing the pointed contact terminalsarrayed in the multilayer film in contact with the electrode surfaces ofthe device under test in the third embodiment of the connection deviceshown in FIG. 6.

FIG. 8 is a cross sectional view showing an essential portion of thefourth embodiment of the connection device of this invention.

FIG. 9 is a cross sectional view showing the contact terminals arrayedon the multilayer film in the fifth embodiment of the connection deviceof this invention.

FIG. 10 is a cross sectional view showing the contact terminals arrayedon the multilayer film in the sixth embodiment of the connection deviceof this invention.

FIG. 11 (a) is a flat view showing an embodiment of the contactterminals and layout wiring formed from polyimide film in the connectiondevice of this invention.

FIG. 11( b) is a perspective view of the same contact terminals andlayout wiring.

FIG. 12( a) is a plan view showing another embodiment of the contactterminals and layout wiring formed from polyimide film in the connectiondevice of this invention.

FIG. 12( b) is a perspective view of the same contact terminals andlayout wiring.

FIG. 13 is cross sectional view showing the shape and dimensions of themultilayer film arrayed with contact terminals in the connection deviceof this invention.

FIGS. 14( a) to 14(e) are cross sectional views showing steps in thefirst half of the manufacturing process for manufacturing the multilayerfilm containing the clamping member and frame for the first throughfourth embodiments of the connection device of this invention.

FIGS. 15( a) to 15(d) are cross sectional views showing steps in thelatter half of the manufacturing process for manufacturing themultilayer film containing the clamping member and frame for the firstthrough fourth embodiments of the connection device of this invention.

FIGS. 16( a) to 16(e) are a cross sectional views showing steps in themanufacturing process for manufacturing the multilayer film containingthe clamping member and frame for the fifth embodiment of the connectiondevice of this invention.

FIGS. 17( a) to 17(e) are cross sectional views showing steps in themanufacturing process for manufacturing the multilayer film containingthe clamping member and frame for the sixth embodiment of the connectiondevice of this invention.

FIG. 18 is a diagram showing an overall concept of the first embodimentof the test system of this invention.

FIG. 19( a) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the seventhembodiment of the connection device of this invention.

FIG. 19( b) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the eighthembodiment of the connection device of this invention.

FIG. 20( a) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the ninthembodiment of the connection device of this invention.

FIG. 20( b) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the tenthembodiment of the connection device of this invention.

FIG. 21( a) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the eleventhembodiment of the connection device of this invention.

FIG. 21( b) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the twelfthembodiment of the connection device of this invention.

FIGS. 22( a) to 22(d) are is a cross sectional views showing the stepsin manufacturing process for manufacturing the multilayer filmcontaining the clamping plate for the first through fourth embodimentsof the connection device of this invention.

FIGS. 23( a) to 23(e) are cross sectional views showing steps in themanufacturing process for manufacturing the multilayer film containingthe clamping member and frame for the fifth through twelfth embodimentsof the connection device of this invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Various embodiments of the connection device and test system of thisinvention will be described with reference to the accompanying drawings.

An LSI semiconductor device (chip) 2, representing the device undertest, is formed in large numbers on a wafer 1 shown in FIG. 1 and lateris detached for use. FIG. 1( a) is a perspective view showing the wafer1 formed with many LSI semiconductor devices (chips). FIG. 1( b) is aperspective view showing one enlarged semiconductor device (chip). Thesurface of the semiconductor device (chip) 2 is arrayed with a pluralityof electrodes 3 along the periphery.

However, along with high integration of the semiconductor device, theelectrodes 3 are placed at an ever greater density and narrower pitch.The pitch of the electrodes is within 0.2 mm and for instance may be0.13 mm, 0.1 mm or less. In terms of high density of electrodeplacement, the electrodes may be from one row to two rows and are evenshowing a trend to be arrayed over the entire surface.

In the connection device (probing device) of this invention, one or aplurality of semiconductor devices from among a plurality ofsemiconductor devices (chips) arrayed on a wafer can simultaneously bestably and reliably contacted with a small contact pressure (about 3 to50 mN per pin) on the oxidized surface of the electrodes, formed forinstance of aluminum or solder with a stable and low resistance value of0.05 to 0.1Ω, and operational tests of each semiconductor device can beperformed by the tester. In other words, the connection device (probingdevice) of this invention can handle devices with a high electrodedensity as well as a narrow pitch, and further can perform testing bysimultaneous probing of many discrete chips and can also performoperational tests with high speed electrical signals (high frequenciesfrom about 100 MHz up to some 10 GHz).

FIG. 2 is a cross sectional view showing an essential portion of thefirst embodiment of the connection device of this invention. In thefirst embodiment of this connection device, a center pivot 41 forms asupport axis having a support member (upper clamp plate) 40, and aspherical member 41 a, which is secured to the lower part of centerpivot 41 and is installed for symmetrical movement back and forth andright and left, is centered on the center pivot 41. The connectiondevice also has spring probes 42 as the pressure application means forapplying a constant and fixed pressing force for upper and lowerdisplacement, a pressing member (press plate) 43, which is subjected toa low load pressing force (about 3 to 50 mN per pin) by way of thespring probes 42, while maintaining a tiltable force by means of thetaper (tilted) 43 c relative to the center pivot 41. The connectiondevice further has a multilayer film 44, a frame 45 clamped to themultilayer film 44, a cushioning layer 46 installed between themultilayer film 44 and the clamping member 43, a contact terminal 47installed in the multilayer film 44, a lead out wire 48 connected to thecontact terminal 47 installed in the multilayer film 44, and a groundlayer 49 installed in the multilayer film 44. The structure for applyinga pressing force on the pressing member 43 with the spring probes 42 isdesigned to obtain a constant low load pressing force from displacementof the tip of the spring probes 42, and use of the spring probe 42 isnot always necessary. The support means (upper clamp plate) 40 is housedin a circuit board 50. The periphery of the multilayer film 44 is formedto extend to the outer side from the frame 45, and this extension bendssmoothly under the outer side of the frame 45 and fastens on the circuitboard 50. In this case, the lead out wire 48 is electrically connectedto an electrode 50 a installed in the circuit board 50. In order to makethis connection to the electrode 50 a of the circuit board 50, a fillet51 filled with metallic plating is installed in the multilayer film 44and the fillet 51 and electrode 50 a can be made to directly contacteach other, or they can be connected with an anisotropic conductivesheet 52 or solder, etc.

The circuit board 50 may be formed of plastic such as polyimide resin orglass-epoxy resin and contains the internal wiring 50 b and the contactterminals 50 c. The electrode 50 a may for instance be connected to aportion of the internal wiring 50 b by the fillet 50 d. The circuitboard 50 and the multilayer film 44 may for instance be fastened byenclosing the multilayer film 44 between the multilayer film clampmember 53 and the circuit board 50 and securing them with a screw 54.

The multilayer film 44 is flammable and preferably is formed with a heatresistant resin as the main constituent. In this embodiment, polyimideresin is utilized. The cushioning layer 46 is formed of a materialhaving elasticity such as an elastomer (polymer material havingresilience similar to rubber). More specifically, silicon rubber or anequivalent is used. A structure to supply gas to a movable sealed spacemay be used for the frame 45 with respect to the clamping member 43.

Also, if the evenness of the tip height of the contact terminal 47 canbe maintained then the cushioning layer 46 can be omitted.

The contact terminal 47, the lead out wire 48 and the ground layer 49are formed of conductive materials. Detailed information on the materialwill be subsequently provided. In order to simplify the explanation,only two contact terminals are shown in FIG. 2 for the lead out wire 48and contact terminal 47; however, in actual use, a plurality of lead outwires 48 and contact terminals 47 are used as will be described lateron.

First of all, in the connection device (probing devices of thisinvention, one or a plurality of semiconductor devices from among aplurality of semiconductor devices (chips) arrayed on a wafer aresimultaneously yet stably and reliably contacted at a low contactpressure (about 3 to 50 mN per pin) on the oxidized surface of theelectrodes, formed for instance of aluminum or solder with a stable andlow resistance value of 0.05 to 0.1Ω. Thus no scribing action is neededas required in the conventional art and the generation of debris fromthe scribing action on the electrode material can be prevented. In otherwords, along with arranging the array of pointed contact terminals 47 tomatch the array of electrodes 3, at the area 44 a with the array ofcontact terminals 47 within the periphery 44 b supported at the frame45, the protuberance 43 a formed on the lower side of clamping member 43functions to stretch the multilayer film 44 enclosing the cushioninglayer 46 to maintain a precise level in parallel with the lower surface43 b eliminating slack in the multilayer film 44 itself, and the pointedtip of the contact terminals 47 arrayed in the projected area 44 aperform low load probing parallel to the electrode 3 (material beingcontacted) such as aluminum or solder, and the pointed contact terminal47 easily breaks through the oxidation on the surface of the electrode 3(material being contacted) and makes secure contact with the lowerconductive metal material at a stable resistance value of 0.05 to 0.1Ω.In particular, at the periphery 44 b supported at the frame 45, theslack in the multilayer film itself is eliminated by the protuberanceenclosing the cushioning layer 46 parallel with the lower surface 43 bmaintained at a precise level by the protuberance 43 a formed in thelower side of the clamping member 43. The amount of projection in thearea 44 a, is determined by an adjusting screw 57 which adjusts theamount of protrusion from the lower surface of the clamping member 43(press plate) by tightening left and right, back and forth centering onthe center pivot 41. In other words, until the lower edge of the screws57 for determining the protrusion amount makes contact with the uppersurface of frame 45, the screw 56 inserted in the hole formed in theclamping member per front and back and left and right centering on thecenter pivot 41 is tightened in the frame 45 so that the protuberance 43a of the clamping member 43 is made to lower and by way of cushioninglayer 46, the area 44 a arrayed with a plurality of contact terminals 47is caused to protrude to eliminate slack in the multilayer film 44. Inthis way, the flatness or level of the plurality of pointed contactterminals 47 can be maintained with a highly precise ±2 μm.

Also, as shown in slightly exaggerated form in FIG. 3, in making thesurfaces 3 a of the electrode 3 (material being contacted) of the singleor plurality of semiconductor devices disposed in parallel with thecorresponding plurality of contact terminals 47, along with maintainingthe clamping member (press plate) 43 in a tiltable state by means of thecenter pivot 41, a constant, fixed pressing force is applied by thespring probe 42, centering on the center pivot 41 installedsymmetrically versus front and back and right and left movement inresponse to vertical displacement of the clamping member 43. In otherwords, a compliance mechanism for applying a low load per each pin isformed by engagement of the center pivot 41 (clamping member supportaxis) and clamping member 43 as well as the symmetrically installedspring probe 42. The follow up and paralleling of the plurality ofpoints of the contact pins 47 with one or a plurality of surfaces 3 a ofthe electrode 3 is performed by this compliance mechanism. As shown inFIG. 2, the center pivot 41 is positioned in the center of the clampingmember 43, and by utilizing the tiltable contact state of the taper(tilt) 43 c installed above the clamping member 43 and the lowerspherical surface 41 a of the center pivot, in the initial state, aninitial specified position can be set by means of the pressing force ofthe spring probe 42. Next, a compliance mechanism has been formed by thecenter pivot 41 (clamping member support axis) and clamping member 43 aswell as the spring probe 42 so that, as shown in FIG. 3, at the timewhen the pointed tips of contact terminals 47 start to contact theelectrodes 3, the taper (tilt) 43 c of the clamping member 43 rubsagainst a portion of the lower spherical surface 41 a of the centerpivot with the axis of the center pivot 41 serving as the central axis.The lower spherical surface 41 a of the center pivot then separates fromthe taper (tilt) 43 c of the clamping member 43, and the clamping member43 then tilts so as to follow up on (trace) the overall surface 3 a ofthe electrode 3, and along with making the surface with the plurality ofpointed contact terminals parallel with the overall surface 3 a of theelectrode 3, variations greater than ±2 μm in the height of theindividual contact terminal points are absorbed by localized warping ofthe cushioning layer 46, and contact with the electrode (material) 3arrayed on the semiconductor wafer 1, with height variations maintainedwithin ±0.5 μm, and uniform, low load, probing (about 3 to 50 mN perpin) can be achieved.

Therefore, as described above, by forming a projection in the multilayerfilm 44 by way of the cushioning layer 46 by means of a protuberance 43a of clamping member 43 for the area 44 arrayed with contact terminals47 for the multilayer film 44, and by making the surface with theplurality of pointed contact terminals 47 parallel with the overallsurface 3 a of the electrode 3, by means of the tiltable support of theclamping member 43 in the center pivot 41, a uniform, low load, probing(about 3 to 50 mN per pin) of a plurality of separate chips cansimultaneously be performed with a stable low resistance value of 0.05to 0.1Ω. Of course, the same kind of probing can also be achieved on onechip.

Also, by installing a ground layer 49 opposite and enclosing theinsulation film 66 (74) for the lead out wiring 48 connected to each ofthe terminals 47 as shown in FIG. 4, appropriate values can be set forthe conductivity ∈r of the insulation film 66 (74), the thickness (gapbetween the lead out wire 48 and the ground layer 49) h and also thewidth w of the lead out wire 48, and by setting the impedance ZO of thelead out wire 48 to about 50Ω, impedance matching with the testercircuit can be achieved. Consequently, distortion and attenuation in theelectrical signals sent via the lead out wire 48 can be prevented, andhigh frequency electrical signals (high frequencies from about 100 MHzup to some 10 GHz) can be utilized with the tester and semiconductordevice under test to perform testing of the device electricalcharacteristics.

As described above, in the multilayer film 44 the impedance of theground layer 49 that encloses the insulation film 66 (74) for the leadout wiring 48 connected to each of the terminals 47 can be matched withthe impedance of the tester circuit at about 50Ω. The length of otherprobes (contact terminals) will only be a contact terminal portion (0.05to 0.5 mm) 47 so that impedance matching with the tester circuit ispossible, distortion in the high speed electrical signals can be reducedand testing of electrical characteristics of the semiconductor deviceunder test can be performed with high speed electrical signals.

FIG. 5 shows an essential portion of the second embodiment of theconnection device of this invention. In this second embodiment of theconnection device, a fillet 51 filled with metallic plating at the upperedge of the lead out wiring 48 positioned below the circuit board 50 atthe boundary of the multilayer film 44 may make direct contact withelectrode 50 a formed on the lower side of the circuit board 50 or maybe connected by an anisotropic conductive sheet 52 or by solder, etc. Inother words, in the second embodiment of this invention, an upper edgecan be formed at the edge of the lead out wire 48 for the multilayerfilm 44 by means of the fillet 51, and connected with the electrode 50 ainstalled at the bottom of the circuit board 50. All other structuresare identical to the first embodiment shown in FIG. 2.

FIG. 6 is a view showing an essential portion of the third embodiment ofthe connection device of this invention. In this third embodiment,instead of the center pivot 41 utilized in the first embodiment,knockpins 55 are utilized to maintain a slightly tilted status for theclamping member 43. More specifically, four knockpins 55 are installedat left and right and back and forth, centered symmetrically around theclamping member 43. These knockpins 55 are inserted in an upwardexpanding taper hole 58 formed in the support member 40 and are fastenedin the clamping member 43. All other structures are identical to thefirst embodiment shown in FIG. 2. In other words, in order that thesurface with the plurality of pointed contact terminals 47 is madeparallel with the overall surface 3 a of the electrode 3 on the singleor plurality of semiconductor devices, as shown slightly exaggerated inFIG. 7, along with each of the knockpins 55 installed in the clampingmember 43 maintaining a tilt capability below the upward expanding taperholes 58 formed in the support member 40, a constant, fixed low loadpressing force (about 3 to 50 mN per pin) is applied by the spring probe42 installed so as to be centered symmetrically front and back and rightand left versus the clamping member 43 in response to verticaldisplacement of the clamping member 43. In other words, a compliancemechanism to apply a low load per pin is formed by the engagementbetween each of the knockpins 55 fastened in the clamping member 43 andthe upward expanding taper holes 58 formed in the support member (upperclamp plate) 40, as well as by the symmetrically installed spring probes42. The follow up and paralleling of the plurality of points of contactpins 47 with one or a plurality of surfaces 3 a of the electrode 3 isperformed by this compliance mechanism. First of all, as shown in FIG.6, the pressing force applied by the spring probe 42 on the clampingmember 43 positions the heads of each knockpin 55 in direct contact withthe upper surface of the support member 40. Next, the compliancemechanism is formed by means of the taper holes 58 formed in the supportmember 40 and each of the knockpins 55 installed in the clamping member43 so that, as shown in FIG. 7, each of the knockpins 55 slide in thetaper holes 58 by means of a uniform pressing force on the clampingmember 43 due to the spring probes 42, and the tilt of the knockpins 55makes the clamping member 43 freely follow up on (trace) the overallsurface 3 a of the electrode 3, and, along with making the surface withthe plurality of pointed contact terminals parallel with the overallsurface 3 a of the electrode 3, variations greater than ±2 μm in theheight of the individual contact terminal points are absorbed bylocalized warping of the cushioning layer 46, and contact performed withthe electrode (material) 3 arrayed on the semiconductor wafer 1 withheight variations maintained within ±0.5 μm, and uniform, low load,probing (about 3 to 50 mN per pin) can be achieved.

FIG. 8 is a cross sectional view showing an essential portion of thefourth embodiment of the connection device of this invention. In thisfourth embodiment of the connection device, a connected fillet 51 filledwith metallic plating at the upper edge of the lead out wiring 48positioned below the circuit board 50 at the boundary of the multilayerfilm 44 may make direct contact with electrode 50 a formed on the lowerside of the circuit board 50 or may be connected by an anisotropicconductive sheet 52 or by solder, etc. In other words, in this fourthembodiment of the invention, the edge of the lead out wire 48 for themultilayer film 44 can be formed on the upper edge by means of thefillet 51, and connected with the electrode 50 a installed at the bottomof the circuit board 50. All other structures are identical to the thirdembodiment shown in FIG. 6.

FIG. 9 is a view showing an essential portion of the fifth embodiment ofthe connection device of this invention. The structure in the fifthembodiment, in the multilayer film 44, for connecting the lead out wires48 and the connection terminals 47 is different from previousembodiments, however it is otherwise configured identically to theconnection devices shown in FIGS. 2, 5, 6 and 8. In other words, in thisfifth embodiment, as shown in FIG. 9, a polyimide film 61 is formed onlyin the area arrayed with the electrodes 3 of the device under test, anda plurality of contact terminals 47 are arrayed to correspond to theelectrodes 3 in the polyimide film 61. The electrodes 62 formed on thepolyimide film 61 connected to the contact terminals 47 are made toconnect to the electrode 69 of the polyimide film 65 forming the leadout wire 48 by means of an anisotropic conductive sheet 70. A multilayerfilm 44 formed with contact terminals 47 is accomplished by anintegrated connection of the anisotropic conductive sheet 70 and thepolyimide film 61. This multilayer film 44 may be formed beforehand forinstance from a wiring film comprised of a polyimide film 65, a layoutwire 48, an intermediate polyimide film 66, a ground layer 49 and apolyimide protective film 68.

FIG. 10 is a view showing an essential portion of the sixth embodimentof the connection device of this invention. The structure of this sixthembodiment for connecting the lead out wires 48 in the multilayer film44, with the connection terminals 47, is different from the previousembodiments, however it is otherwise configured identically to theconnection devices for the embodiments shown in FIG. 2, 5, 6 and 8. Inother words, in this sixth embodiment, as shown in FIG. 10, the contactterminals 47 are formed of the multilayer film 44 by making the contactterminals 47 contact the electrode 69 of the polyimide film 65 formed ofthe lead out wire 48, by means of an anisotropic conductive sheet 70.This multilayer film 44 may be formed beforehand for instance from awiring film comprised of a polyimide film 65, a layout wire 48, anintermediate polyimide film 66, a ground layer 49 and a polyimideprotective film 68.

FIG. 19( a) is a view showing an essential portion of the seventhembodiment of the connection device of this invention. The structure ofthis sixth embodiment for connecting the lead out wires 48 in themultilayer film 44, with the connection terminals 47, is different fromthe previous embodiments, however it is otherwise configured identicallyto the connection devices for the embodiments shown in FIGS. 2, 5, 6 and8. In other words, as shown in FIG. 19( a), the seventh embodiment has aplurality of contact terminals 47 arrayed in the mold 80 of the siliconwafer, as described later with reference to FIG. 17 (b), to correspondto the electrodes 3 of the device under test. The electrodes 200 formedas an integrated piece with the contact terminals are connected by wayof the solder 201 to the electrode 69 formed from the polyimide film 65forming the lead out wire 48, and the contact terminals 47 formed withthe multilayer film 44 by means of the integrated coupling of thepolyimide film 65, the solder 201 and the electrode 200. This multilayerfilm 44 may be formed beforehand for instance from a wiring filmcomprised of a polyimide film 65, a layout wire 48, an intermediatepolyimide film 66, a ground layer 49 and a polyimide protective film 68.The electrodes 69 of the polyimide film 65 and the electrodes 200integrated into one piece with the contact terminals 47 are covered witha resin 202 which forms a protective film. An epoxy type resin or anacrylic type thermosetting resin or a thermoplastic resin may forinstance be utilized as the resin 202. As a method of forming theprotective film of resin 202, after, for instance, soldering theelectrode 69 of the polyimide film 65 with the electrode 200 of thecontact terminals 47, a resin 202 is poured from a dispenser into thegap between the silicon wafer mold 80 and the polyimide film 65, theresin is and then formed by thermosetting, or alternatively the resin202 can be injected between the silicon wafer mold 80 constituting thecontact terminals 47, and the multilayer film 44 formed the solder 201and heat pressurization performed, and the resin 202 layer is thenformed by connecting the solder 201 between the electrode 69 and theelectrode 200. A crystallized tin/lead mixture or a tin-lead solder mayused as the solder used in forming the protective film.

The resin 202 can also be omitted.

FIG. 19 (b) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the eighthembodiment of the connection device of this invention. The structure ofthis eighth embodiment for connecting the lead out wires 48 in themultilayer film 44, with the connection terminals 47, is different fromthe previous embodiments, however it is otherwise configured identicallyto the connection devices for the embodiments shown in FIGS. 2, 5, 6 and8. In other words, as shown in FIG. 19 (b) of the eighth embodiment, amultilayer film 44 formed with contact terminals 47 is produced bymaking the contact terminals 47 contact, by means of the solder 201, theelectrode 69 of the polyimide film 65 formed of the lead out wire 48.This multilayer film 44 may be formed beforehand for instance from awiring film comprised of a polyimide film 65, a layout wire 48, anintermediate polyimide film 66, a ground layer 49 and a polyimideprotective film 68. The electrodes 69 of the polyimide film 65 and theelectrodes 200 integrated into one piece with the contact terminals 47are covered with a resin 202 which forms a protective film. An epoxytype resin or an acrylic type thermosetting resin or a thermoplasticresin may for instance be utilized as the resin 202. A crystallizedtin/lead mixture or a tin-lead solder may used as the solder used informing the protective film.

FIG. 20 (a) is a cross sectional view showing a portion of themultilayer film arrayed with the contact terminals in the ninthembodiment of the connection device of this invention. The structure ofthis ninth embodiment for connecting the lead out wires 48 in themultilayer film 44 with the connection terminals 47 is different fromthe previous embodiments, however it is otherwise configured identicallyto the connection devices for the embodiments shown in FIGS. 2, 5, 6 and8. In other words, as shown in FIG. 20( a), the ninth embodiment has aplurality of contact terminals 47 arrayed in the mold 80 of the siliconwafer, as described later with reference to FIG. 17( b), to correspondto the electrodes 3 of the device under test, and the electrodes 200formed in an integrated piece with the contact terminals 200 areconnected to the solder fillet electrode 203 formed in the polyimidefilm 65 forming the lead out wire 48 and then forming the multilayerfilm 44 comprising contact terminals 47 by means of the integratedcoupling of the polyimide film 65, the solder fillet electrode 203 andthe electrode 200. The structure of this multilayer film 44 and theprotective film of resin 202 are the same as the seventh embodiment. Thesolder fillet electrode 203 is made by forming solder plating in thelead out wiring 48.

FIG. 20 (b) is a view showing an essential portion of the multilayerfilm arrayed with the contact terminals in the tenth embodiment of theconnection device of this invention. In this tenth embodiment of theconnection device, the portion connecting the contact terminals 47 andthe lead out wiring 48 in the multilayer film 44 differs in connectingdirectly on the contact terminals 47, but otherwise it is the same asthe ninth embodiment in FIG. 20( a) with the same structure for theembodiment of the connection device shown in FIGS. 2, 5, 6 and 8.

FIG. 21 (a) is a view showing a essential portion of the multilayer filmarrayed with the contact terminals in the eleventh embodiment of theconnection device of this invention. The structure of this tenthembodiment for connecting the lead out wires 48 in the multilayer film44 with the connection terminals 47 is different from the previousembodiments, however it is otherwise configured identically to theconnection devices for the embodiments shown in FIGS. 2, 5, 6 and 8. Inother words, as shown in FIG. 21 (a) the eleventh embodiment has aplurality of contact terminals 47 arrayed in the mold 80 of the siliconwafer, as described later with reference to FIG. 17( b), to correspondto the electrodes 3 of the device under test, tin plating 204 formed onthe surface of the electrodes 200 integrated with each contact terminal,and gold plating 205 formed on the electrode 69 of the polyimide film 65forming the lead out wire 48 are subjected to heat expansion, connectedby forming a lead alloy and a multilayer film 44 comprising the contactterminals 47 formed by an integration of the polyimide film 65 and theelectrode 200.

This multilayer film 44 may be formed be forehand for instance from awiring film comprised of a polyimide film 65, a lead out wire 48, anintermediate polyimide film 66, a ground layer 49 and a polyimideprotective film 68.

The tin plating 204 can be gold plating and the gold plating 205 can betin plating so that a lead/gold alloy for heat expansion can be formedby mutual substitution of materials.

FIG. 21( b) is a view showing an essential portion of the multilayerfilm arrayed with the contact terminals in the twelfth embodiment of theconnection device of this invention. In this twelfth embodiment of theconnection device, the portion connecting the contact terminals 47 andthe lead out wiring 48 in the multilayer film 44 differs in connectingdirectly on the contact terminals 47, but otherwise it is the same asthe eleventh embodiment in FIG. 2( a) with the same structure for theembodiment of the connection device shown in FIGS. 2, 5, 6 and 8.

In the above mentioned embodiments 1 through 12, the contact terminals47 were formed of conductive material. The contact terminals 47 wereconsequently of harder material at that portion than the multilayer film(wiring film) 44 so that more satisfactory contact could be made when indirect contact with the electrodes of the item under test.

The placement of the contact terminals as well as the wiring patterns ofthe lead out wiring 48 in these connection devices were structured invarious types corresponding to the electrode pattern of the item undertest such as a semiconductor integrated circuit. The first and secondembodiments of these patterns are shown in FIG. 11 and FIG. 12.

FIG. 11 (a) is a flat view showing an embodiment of the contactterminals and layout wiring formed from polyimide film. FIG. 11 (b) is aperspective view of the same contact terminals and layout wiring showingthe multilayer film in a bent state. FIG. 12 (a) is a flat view showinganother embodiment of the contact terminals and layout wiring formedfrom polyimide film. FIG. 12( b) is an oblique view of the same contactterminals and layout wiring showing the multilayer film in a bent state.In these figures, in order to simplify the descriptions, the number ofcontact terminals and lead out wires are reduced and are displayed at alow density. In actual use of course, a plurality of contact terminalscan be installed and a high density configuration may be used.

In the connection device as shown for example in FIG. 11( a), 11 (b) andFIGS. 12( a) and 12(b), on the multilayer film 44 comprised of polyimideresin, the lead out wiring 48 is connected at one end to the contactterminals 47 installed at positions corresponding to the electrodes 3 ofthe item under test, and the lead out wiring 48 is connected at theother end to the fillet 51 installed at the periphery of the multifilmlayer 44. This lead out wiring 48 can be wired in variousconfigurations. The wiring for instance can be laid out in one directionor can be laid out in a radial shape. More specifically, the multilayerfilm 44 is formed in a square shape and the lead out wiring 48 connectedto the fillets 51 installed at all sides of the square shapes on themultilayer film 44 as shown in the first embodiment in FIGS. 12( a) and12(b). The multilayer film 44 is formed in a rectangular shape in FIGS.11 (a) and 11 (b) in the second embodiment and connects to the fillets51 on both edges.

Next, the concepts for manufacturing the connection devices of theseembodiments will be described.

As a method of laying out the wiring for the connection device fortransmitting electrical signals to the test unit, when for instance, theitem under test is wafer (LSI) formed with electrodes on the surface ofthe LSI, the process is as described next. First of all, as shown inFIG. 11 (a) and FIG. 12 (a), a contact terminal mold 102 for siliconwafers one size larger than the area 101 of the applicable LSI wafer isutilized, a mask of silicon dioxide is formed by anisotropic etching ofa silicon wafer as a mold and the holes used for forming the contactterminals 47 in the area 101 the same as the applicable LSI water. Then,using this now fabricated mold, the protuberances are made for formingthe contact terminal 47. Further, a multilayer film 44 comprised of apolyimide film and a lead out wiring 48 is connected to the surface ofthe contact terminal mold 102. An opening 103 is formed in themultilayer film 44 as needed as shown in FIG. 11 (a). Then, the areaformed for the contact terminals 47 is secured to the frame 45 on therear of the multilayer film 44 corresponding to the test area 101 on theapplicable LSI wafer as shown in FIG. 11 (b) or FIG. 12 (b) and bent ina polygonal shape. Still further, a cushioning layer 46 is fit inwardsbetween the clamping member 43 and the multilayer film 44 with the frameas shown in FIG. 2, FIG. 5, FIG. 6 and FIG. 8, and, after installing itinto an integrated shape, the contact terminal mold 102 is then removed,and an upper clamp board 40 as well as a circuit board 50 is placedthereon. The fillet 51 lead out wiring 48 is connected to the electrodes50 a of said circuit board 50 with a conductive sheet 52 or solder andthe multilayer film clamp member 53 is connected by screws 54 to thecircuit board 50.

The above example is directed to the case where contact is made in onebatch with all electrodes of the semiconductor devices formed on thewafer of the item under test but this invention is not limited to thisexample. The multilayer film for instance may be manufactured with anarea smaller than the wafer size for a connection device for instancefor testing semiconductor devices separately or simultaneously testingan optional number of semiconductor devices.

The manufacture and the manufacturing method for contact terminals ofthe first embodiment of the connection device of this invention will bedescribed next.

The contact terminal portion shown in FIG. 13 has a polyimide film 71 inthe bottom layer as the multilayer film 44 and also has a bump 72 forforming the protuberance (tip), and a plated film 73 in that tip. Onesurface (side facing the board) of the polyimide film 71 is formed by alead out wiring 48, a polyimide film 74, a ground layer 49 and apolyimide protective film 75. The lead out wiring 48 is installed tomake that end contact the bump 72. The contact terminal 47 is formed forinstance, with a point in a pyramid shaped bump 72 and with a platingfilm 73 formed on the surface of the point of this bump 72. This bump 72is formed for instance of nickel which has a high degree of hardness andis easily plated. The plating film 73 is formed of rhodium and is evenharder than the nickel film. The reason for utilizing rhodium as theplating film 73 is that the hardness of the rhodium is considerablygreater than that of the nickel film.

Typical dimensions for the contact terminal in the first embodiment ofthe connection device of this invention are shown in FIG. 13. Morespecifically, to be compatible with semiconductor devices having anelectrode with a narrow pitch less than 0.2 mm, such as for example 0.13mm or 0.1 mm, the ground layer 49 and the polyimide protective film 75have a thickness of approximately 5 μm, the polyimide film 74 has athickness of approximately 50 μm, the polyimide film 71 has a thicknessof approximately 20 μm, the tip of the contact terminal 47 has a heightof approximately 28 μm, and the width at the bottom of the tip isapproximately 40 μm. In the first embodiment, one side of the lowerportion is comprised of a pointed contact terminal with a point in afour-sided pyramid shape of for example 10 to 60 μm. This die for thefour-sided pyramid is made as a pattern with lithographic techniques andso the size can be determined with high precision. A sharply definedshape can be achieved by forming it with anisotropic etching. The tip inparticular, can be made in a pointed shape and is the same in the otherembodiments.

The contact terminal 47 of this embodiment is further capable of easilyadapting to semiconductor devices with an electrode pitch narrower than0.1 mm, to a range of 10 to 20 μm. More specifically, one side of thebottom of the contact terminal 47 can easily be formed to a size of 5μm. In terms of the multilayer film, the height of the contact terminal47 can be achieved at a precision within ±2 μm during forming, and, as aresult, even when utilizing the clamping member (clamp plate) 43 on thearea 44 a arrayed with a plurality of contact terminals 47 to enclosethe cushioning layer 46 and cause a projection to eliminate slack in themultilayer film itself, the height precision of the contact terminal 47can be acquired within a precision of +2 μm. Therefore stable and lowload probing (about 3 to 50 mN per pin) of electrodes 3 array on asemiconductor device can be achieved.

The reason for selecting a pointed shape for the tip of the contactterminal 47 is related as follows.

An oxidized surface is formed when utilizing material such as aluminumfor the electrode 3 of the item under test so that the resistance isconsequently unstable when making contact. In this kind of electrode 3,a stable resistance value can be obtained when the fluctuation inresistance is less than 0.5Ω so that a tip is required for the contactterminal 47 that can break through the oxidized surface of the electrode3 and maintain satisfactory contact. As described in the prior art, whenusing a semicircular shape for the point of the contact terminal 47, acontact pressure greater than 300 mN per pin is required in order to rubthe electrode against the contact terminals. On the other hand, when thetip of the contact terminal has a flat shape of a diameter within arange of 10 to 30 μm, a contact pressure greater than 100 mN per pin isrequired in order to rub the electrode against the contact terminals.Consequently, electrode material debris including an oxidized layer isgenerated, causing penetration of foreign objects and electrical shortsbetween the wiring, and a large contact pressure in excess of 100 mN cancause damage to the electrode or to the element directly below theelectrode.

However, when utilizing a contact terminal 47 with a pointed tip as inthe embodiment of this invention, a contact pressure of approximately 3to 50 mN per pin is able to achieve electrical continuity at a stableresistance within 0.5Ω just with the pressing force and does not scarthe electrode 3. Consequently, a low pin pressure is sufficient to makecontact with the electrode so that no damage is applied to the electrodeor to the element directly below the electrode. Also, the force neededto apply pin pressure to all of the contact terminals can be reduced. Asa result, the load resistance of the prober drive device can be reducedin the equipment using this connection device and manufacturing costscan therefore be reduced.

If a load of 100 mN can be applied per pin by sticking the electrodewith a four sided pyramid structure having a base with one side of about40 μm, and if the tip is smaller than 30 μm, then a pointed shape neednot be used for the contact terminal. However, for the above mentionedreasons, the tip area as much as possible should be reduced to obtain apoint with a surface area reduced to 5 μm or less.

Also, using a contact terminal 47 with a pointed tip assures that thereis no striking or gouging of the electrode 3, and a low push pressure ofapproximately 3 to 50 mN per pin is sufficient for making contact sothat no debris is generated from the electrode material. As a result,there is no need for a cleaning process to remove electrode materialdebris after probing and thus the manufacturing cost can be reduced.

Next, the manufacturing process for forming the connection device(probing device) is shown in FIG. 2, FIG. 5, FIG. 6 and FIG. 8 whilereferring to FIG. 14 and FIG. 15. In particular, in the manufacturingprocess for forming the connection device shown in FIG. 2, themanufacturing process sequence of FIG. 14 and FIG. 15 is used forshowing utilization of a four-sided pyramid hole formed by anisotropicetching on the die for silicon wafer 80, in a state with a thin filmformed with the four-sided pyramid contact terminal point, a freelyadjustable connection device can be assembled by means of the cushioninglayer 46 and the spring probe 42 by way of the center pivot 41.

The process is first implemented while referring to FIG. 14( a). In thisprocess, a silicon dioxide film 81 is formed to approximately 0.5 μm byheat oxidizing on both sides of a silicon wafer 80 (100) with athickness of 0.2 to 0.6 mm. Next, etching of the silicon dioxide film 81is performed by photo-resist masking. Anisotropic etching is performedon the silicon wafer 80 using the silicon dioxide film 81 as a mask andthe hole 80 a is etched in a four-sided pyramid shape enclosed by the(111) surface. In other words, the four-sided pyramid shaped hole 80 ais etched within an enclosed (111) surface by anisotropic etching usingthe silicon dioxide film 81 as a mask.

Next, the process shown in FIG. 14( b) is implemented. In this process,a silicon dioxide film 82 is formed to about 0.5 μm by heat-oxidizing inwet oxygen on the surface (111) of the anisotropically etched siliconwafer 80. Next a conductive coating 83 is formed over the silicondioxide film 82 and then a polyimide film 84 (71) is formed as themultilayer film on the surface of the conductive coating 83. After thenremoving the polyimide film 84 (71) down to a surface of the conductivecoating 83 at the positions where the contact terminals 47 are to beformed, electrical plating using high hardness nickel as the mainconstituent is performed with the conductive coating 83 as the electrodeat the exposed openings where the polyimide film 84 (71) was removed andthe bump 85 (72) is formed as the contact terminal. Besides nickel as amaterial for forming the bump 85 (72) as the electrically plated contactterminal 47, copper has been proposed, however copper (CU) is relativelysoft and cannot be used alone.

Next, the process shown in FIG. 14( c) is implemented. In this process,a copper layer is formed by a sputtering process or vapor depositionprocess on the surface of the polyimide film 84 and the bump 85 (72) toform a conductive film with a thickness of approximately 1 micrometer.The layout wiring 48 is formed by a photoresist process to form thewiring on this surface, and an intermediate polyimide film 86 (74) isthen formed on the surface of the polyimide film 84. Next, a groundlayer 49 is formed on this surface and a polyimide protective film 87(75) further is formed over that surface.

The process shown in FIG. 14( d) is next implemented. In this process, aframe 45 is positioned and bonded to the surface of the protectivepolyimide film 87 (75) and a silicon coating material is next suppliedinside the frame 45 as the cushioning layer 46. In this embodiment, anelastomer is utilized as a silicon coating material with, for instance,a hardness (JISA) of 15 to 70 and a thickness of 0.5 to 3 mm. However,the coating material is not restricted to elastomers. The elastomer maybe used as an elastomer in a sheet shape and the elastomer itself neednot be used. The cushioning layer 46 functions to alleviate the overallimpact of contact from the points of the plurality of contact terminals47 during contact with the electrodes 3 arrayed on the semiconductorwafer 1. The cushioning layer 46 also deforms locally to absorbvariations greater than ±2 μm in the height of the individual contactterminals 47 in order to ensure that uniform contact is achieved withvariations within ±0.5 μm in the height of the electrodes 3 arrayed onthe semiconductor wafer 1. The task of alleviating the overall impact isa small task in this particular embodiment of the invention since theload imposed on each pin is low. Accordingly, if variation in the heightof the contact terminals 47 can be maintained within +0.5 μm, then thecushioning layer is not always necessary. As one method to achieveheight variations within 10.5 μm for the points of the contact terminals47, a contact terminal 47 group formed in the multilayer film 44 may bepressed down in one batch on a silicon substrate maintained at aprescribed level.

The process shown in FIG. 14( e) is next implemented. In this process,the clamping member 43 is secured to the frame 45 with a screw 56.

Next, the process shown in FIG. 15( a) is implemented. In this process,a silicon wafer 80 is mounted via the 0-ring 89 between the stainlesssteel lid 90 and the multilayer film 44 screwed to the frame 45 on theclamping member 43, in a stainless clamping jig 88 for etching of thesilicon wafer 80 used as the die.

The process shown in FIG. 15( b) is next implemented. In this process,etching removal is performed for the silicon wafer 80 and the conductivecovering 83.

Next, the process shown in FIG. 15( c) is implemented. In this process,the multilayer film 44 screwed to the frame 45 on the clamping member 43is removed from the lid 90, 0-ring 89 and clamping jig 88. Next, rhodiumplating 91 (73) is performed and then positioning and bonding of themultilayer film member 53 on the periphery of the multilayer filmprotective polyimide film 87 (75) is performed. The reason forperforming rhodium plating 91 (73) on the surface of the bump 85 (72) ofthe contact terminals 47, comprised of material such as nickel, is thatthe material of the electrode 3 such as solder or aluminum is less proneto adhere, the hardness is greater than the material (nickel) of thebump 85 (72), contacts are not prone to oxidize and have a stableresistance value, and plating is easy to perform.

Next, the process shown in FIG. 15( d) is implemented. In this process,the multilayer film is trimmed to the outer profile design dimensionsand next the gap between the frame 45 and the clamping member (clampplate) 43 is adjusted with the screw 57, and screw tightening of screw56 makes the tip of the screw 57 come in direct contact with the topedge of the frame 45 so that the clamp member 43 advances with respectto the frame 45, and the pressing action of the clamping member 43 onthe area 44 a arrayed with the contact terminals 47 on the multilayerfilm 44, by way of the cushioning layer 46, causes an appropriatestretching in the multilayer film 44 film itself, so that slack iseliminated in multilayer film 44 itself and the level of the tips of thecontact terminals can be maintained within a precision of ±2 μm.

Next, the assembly process is implemented and the connection device(probing device) comprised of a thin-film probe card is completed. Morespecifically, as shown in FIG. 2, the multilayer film 44 is installedonto the circuit board 50. Next, the taper (tilt) 43 c is installed ontothe upper surface of the clamping member 43 in a state where the lowerspherical surface 41 a of the center pivot is engaged with the taper(tilt) 43 c. Next, along with installing the center pivot 41 to thesupport member (upper clamp plate) 40 attached to the spring probe 42,the circuit board 50 attached to the multilayer film 44 is installed atthe periphery of the support member 40 to comprise the thin-film probecard.

When assembling the connection device (probing device) shown in FIG. 5,first of all, after installing the center pivot 41 to the clampingmember 43, the multilayer film 44 can be attached to the circuit board50.

When manufacturing the thin-film probe card of FIG. 6 or FIG. 8, otherthan installing knockpins 55 instead of a center pivot 41, onto theclamping member 43, the manufacturing of the thin-film probe card can beperformed with the same processes as shown in FIG. 14 and FIG. 15.

The etching removal process for the silicon wafer 80 shown in FIGS. 15(a) and 15 (b), may be implemented at a stage prior to bonding to theframe 45 shown in FIG. 14 (c) or the bonding may be implemented at astage (stage for bonding only of frame 45 shown in FIG. 14( c)) prior toinstallation of the clamping member 43 shown in FIG. 14 (d).

The level of the tip height of the contact terminals 47 can bemaintained, even without the cushioning layer 46, by utilizing a clampplate 210 that integrates the frame 45 and the clamping member 43 sothat the cushioning layer 46 is not needed.

The cushioning layer 46 is omitted in FIG. 22 and the working example ofthe manufacturing process utilizes the clamp plate 210.

In the manufacturing process utilizing the clamp plate 210, the processshown in FIG. 22( a) is implemented after the manufacturing processshown in FIG. 14( c) has been implemented. In this process, the clampplate 210 and the multilayer film clamp member 53 in the periphery arealigned and bonded to the surface of the protective polyimide film 87(75).

Next, the process in FIG. 22 (b) is implemented. In this process, asilicon wafer 80 is mounted via the 0-ring 89 between the stainlesssteel lid 90 and the multilayer film 44 clamped to the frame 45 on theclamping member 43, in a stainless clamping jig 88 for etching of thesilicon wafer 80 used as the die.

Next, the process in FIG. 22( c) is implemented. In this process,etching removal is performed for the silicon wafer 80 and the conductivecovering 83.

Next, the process shown in FIG. 22( d) is implemented. In this process,the multilayer film 44 screwed to the frame 45 on the clamping member 43is removed from the lid 90, 0-ring 89 and clamping jig 88. Next, therhodium plating 91 (73) is applied and the multilayer film 44 trimmed tothe outer profile design dimensions.

The assembly process is implemented the same as in FIG. 15 and theconnection device (probing device) comprised of a thin-film probe cardis completed.

The manufacturing process for forming the connection device (probingdevice) shown in FIG. 9 is next described while referring to FIG. 16.Processes identical to those in FIG. 14 and FIG. 15 are omitted from thefollowing description.

As shown in FIG. 16( a), a conductive coating 83 is formed on thesilicon dioxide film 82 on the surface of the anistropically etchedwafer 80 shown previously in FIG. 14 (b). Next, after plating thepolyimide film 84 (61) in the openings in the surface of the conductivecoating 83 and forming the bump 85 for the contact terminals, a copperlayer is formed by sputtering or physical vapor deposition methods tocreate a conductive film of approximately 1 micrometer thickness on thesurface of the polyimide film 84 (61) and the bump (85) and theelectrodes 62 formed by photoresist masking to form electrodes on thatsurface.

Next, as shown in FIG. 16 (b), the electrode 62 is connected by aconductive anisotropic sheet 70 to the fillet 69 of the multifilm layer44 previously formed with a lead out wiring 48 to design profiledimensions. This multilayer film 44 may be formed beforehand forinstance from a wiring film comprised of a polyimide film 65, a lead outwire 48, an intermediate polyimide film 66, a ground layer 49 and apolyimide protective film 68. When connecting the fillet 69 with theelectrode 62, anisolm (Hitachi Chemical Co., Ltd.) may be used as theanisotropic conductive sheet 70 or solder may be utilized for theconnection.

Next, as shown in FIG. 16( c), a multilayer film 44 formed of contactterminals 47 is obtained by removing the silicon wafer 80.

As methods for etch removing the silicon wafer 80 formed with contactterminals 47, a method for etching removal of silicon and silicondioxide or performing selective etch removal of chromium when utilizedas the conductive covering 83, may be used to directly peel away thepolyimide film 84 formed with contact terminals from the silicon wafer80 whose surface was oxidized when used as the die for the contactterminals and formed with silicon oxide layer 82. Either of thesemethods is suitable for use.

In the method for selectively etching removal of the chromium, asolution mixture for instance of aluminum chloride, water of hydration,hydrochloric acid and water may be prepared and etching performed at 50°C. for 4 hours.

Also, as a method for removing the silicon wafer 80 formed with contactterminals 47, rare earth metals such as rhodium or gold may be utilizedas the conductive covering 83, and a silicon dioxide film is formed onthe surface, and mechanical peeling is then performed at the boundarywith the conductive covering 83.

Next, as shown in FIG. 16 (d), the frame 45 and the clamping member 53are position-aligned and bonded on the surface of the protectivepolyimide film 68 and rhodium plating of the contact terminals 47 isthen performed.

Next, as shown in FIG. 16( e), a silicon coating material is nextsupplied inside the frame 45 as the cushioning layer 46 and isscrew-clamped to the clamping member 43 at the frame 45, the gap betweenthe frame 45 and the clamping member 43 narrowed and the slack in themultilayer film 44 itself is eliminated by pressing via the cushioninglayer 46 with the clamping member 43 on the area 44 a arrayed with thecontact terminals 47 in the multilayer film 44, so that a levelness ofthe tips of the contact terminals 47 can be maintained within aprecision of ±2 μm.

An elastomer in a sheet shape may be used as the cushioning layer 46 orthe cushioning layer 46 may be omitted.

Next, as shown in FIG. 2, the multilayer film 44 is attached to thecircuit board 50, the center pivot 41 is installed to the clampingmember 43 and the thin-film probe card is thus completed.

When assembling the connection device (probing device) shown in FIG. 5,after first attaching the center pivot 41 to the clamping member 43, themultilayer film 44 may be installed to the circuit board 50.

In the manufacturing method shown in FIG. 16, a conductive anisotropicsheet 70 was used to achieve electrical continuity between the fillet 69on the multilayer film 44 and the electrode 62 formed on the bump 85 forthe contact terminals however, continuity may also be achieved withsolder or a metallic alloy such as Sn—Ag (tin-silver) or Sn—Au(tin-gold).

The manufacturing process shown in FIG. 10 for forming the connectiondevice (probing device) will be described next while referring to FIGS.17( a) and 17(b). Processes identical to those in FIGS. 14( a)-14(e) andFIGS. 15( a)-15(d) are omitted from the following description.

As shown in FIG. 17( a), a conductive coating 83 is formed on thesilicon dioxide film 82 on the surface of the anistropically etchedwafer 80 shown previously in FIG. 14( b). Next, after plating thepolyimide film 84 in the openings in the surface of the conductivecoating 83, the bumps 85 for the contact terminals are formed.

Next, the etching removal method for the polyimide film 84 is carriedout as shown in FIG. 17( b).

As shown in FIG. 17( c), the lead out wire 48 is formed beforehand, andthe bumps 85 for the contact terminals are connected by way of theconductive anisotropic sheet 70 to the fillet 69 on the wiring film 48made to design profile dimensions.

Next, in FIG. 17 (d), the multilayer film 44 with contact terminals 47is formed on the wiring film 64 by etch removal of the silicon wafer 80.

As shown next in FIG. 17( e), an identical structure is formed, in aprocess identical to the process previously described with reference toFIG. 16( e).

A description of the subsequent processes is omitted since theseprocesses are identical to the processes shown previously in FIGS. 16(a)-16(e).

In the manufacturing method shown in FIGS. 17( a)-17(e), a conductiveanisotropic sheet 70 was used to achieve electrical continuity betweenthe fillet 69 on the multilayer film 44 and the bump 85 for the contactterminals; however, continuity may of course also be achieved withsolder or a metallic alloy such as Sn—Ag (tin-silver) or Sn—Au(tin-gold).

The manufacturing process shown in FIGS. 19( a)-19(b), for forming theconnection device (probing device) will be described next whilereferring to FIGS. 23( a)-23(e). Processes identical to those in FIGS.14( a)-14(e) and FIGS. 15( a)-15(d) are omitted from the followingdescription.

As shown in FIG. 23 (a), a conductive coating 83 is formed on thesilicon dioxide film 82 on the surface of the anistropically etchedwafer 80 shown previously in FIG. 14( b). Next, after plating thepolyimide film 84 in the openings in the surface of the conductivecoating 83, the bumps 85 are formed in an integrated piece with theelectrodes 200, and gold plating is formed on the electrodes 200.

Next, the etching removal method for the polyimide film 84 is carriedour as shown in FIG. 23( b).

As shown in FIG. 23 (c), a lead out wiring 48, formed beforehand, andthe electrode 200 for the contact terminals are connected by way ofsolder 201 to the fillet 69 of the multilayer film 44 made to the designouter profile dimensions. The frame 45 is bonded to the multilayer film44, and next, the silicon coating material is supplied as the cushioninglayer 46 into the frame 45.

Next, the process of FIG. 23 (d), identical to the process shown in FIG.14( e) is implemented.

In this process, a silicon wafer 80, with the multilayer film 44 clampedto the frame 45 on the clamping member 43 by means of the screw 56, ismounted via the 0-ring 89 between the stainless steel lid 90, in astainless clamping jig 88, and etching removal is performed for thesilicon wafer 80 and the conductive covering 83.

Next, the process shown in FIG. 23( e) is implemented. In this process,the multilayer film 44 screw-clamped to the frame 45 to the clampingmember 43 is removed from the lid 90, 0-ring 89 and the clamping jig 88.Next, the rhodium plating 91 is applied, the multifilm clamping member54 is position-aligned and bonded with the periphery of the protectivepolyimide film 87 for the multilayer film, and the multilayer film 44 isthen trimmed to the outer profile design dimensions. The gap between theframe 45 and the clamping member (clamp plate) 43 is next adjusted withthe screw 57, and screw tightening of screw 56 makes the tip of thescrew 57 come in direct contact with the top edge of the frame 45 sothat the clamp member 43 advances with respect to the frame 45, and thepressing action of the clamping member 43 on the area 44 a arrayed withthe contact terminals 47 on the multilayer film 44, by way of thecushioning layer 46, causes an appropriate stretching in the multilayerfilm itself so that slack is eliminated in the multilayer film 44 andlevelness of the types of the contact terminals can be maintained.

The assembly process is next implemented and the connection device(probing device) comprised of a thin-film probe card is completed.

In the manufacturing method shown in FIG. 23, a solder 201 was used toachieve electrical continuity with the fillet 69 of the multilayer film44, and the electrode 200 for the contact terminals, however, a solderfillet electrode 203 of FIG. 20 (a), FIG. 20 (b) or a metal alloy suchas Sn—Au (tin-gold) of FIG. 21( a), FIG. 21( b) may be used to achieveelectrical continuity.

A manufacturing process for removal by etching of the silicon wafer 80was shown in FIG. 23, however, as was previously related, afterconnecting the electrode 200 for the contact terminals to the multilayerfilm 44 with solder or tin/gold alloys as in FIG. 23 (c), by usingchromium as the conductive coating 83 and by selective etching removalusing chromium, the surface of the silicon wafer utilized as the die forthe contact terminals can be oxidized and needless to say, the contactterminals 47 can be directly peeled away from the silicon wafer 80formed with a silicon dioxide film 82.

A description of the testing of electrical characteristics of asemiconductor device (chip) under test by utilizing the connectiondevice (probing device) of the above described invention will bedescribed next with reference to FIG. 18.

FIG. 18 is an overall concept view showing the first embodiment of thetest system of this invention.

This test system is comprised of a wafer prober for manufacture ofsemiconductor devices. This test system is comprised of a materialsupport system 160 for supporting the semiconductor wafer 1 as the itemunder test, a probe system 120 for making contact with the electrode 3of the item under test and for performing an exchange of electricalsignals, a drive control system 150 for controlling the operation of thematerial support system 160, a temperature control system 140 forperforming temperature control of the item under test, and a tester 170for testing electrical characteristics of the semiconductor device(chip) 2. The semiconductor wafer 1 is arrayed with a plurality ofsemiconductor devices (chip) 2, and on the surface of each of thesemiconductor devices (chip) 2, a plurality of electrodes 3 serving asexternal connection electrodes, are arrayed at a high density and anarrow pitch due to the high integration of semiconductor devices. Thematerial support system 160 has a support block 162 mounted largelyhorizontally and mounted to allow free installation and removal of thesemiconductor wafer 1, a vertical axis 164 mounted perpendicularly tosupport the support block 162, a vertical drive section 165 to drive thevertical axis 164 up and down, and an X-Y stage 167 to support thevertical drive section 165. The X-Y stage 167 is clamped to the base166. The vertical drive section 165 is comprised of for instance astepping motor, etc. The positioning operation for vertical andhorizontal directions is performed by combining movement within thehorizontal plane of the X-Y stage 167, and the up and down movement ofthe vertical drive section 165, etc. The support block 162 is installedwith a swivel mechanism not shown in the drawing, and the support block162 is capable of swivel displacement within the horizontal plane.

The probe system 120 is installed above the support block 162. In otherwords, the connection device 120 a and the circuit board 50 shown inFIG. 2 or FIG. 5 or FIG. 6 or FIG. 8 or FIG. 9 or FIG. 10 are installedat positions parallel to the support block 162. Inside this connectiondevice 120 a, a multilayer film 44 having contact terminals 47, acushioning layer 46, a frame 45, a clamping member (clamp plate) 43, acenter pivot 41, a spring probe 42 and a support member (upper clampplate) 40 are integrated as one unit. Each of the contact terminals 47are connected to the fillets 50 d and the electrodes 50 a of the circuitboard 50 by way of the lead out wiring 48 attached to the multilayerfilm 44 of the connection device 120 a, and these contact terminals 47are also connected to the electrodes 50C installed on the circuit board50 by way of the internal wiring 50 b. In this embodiment, the contactterminal 50 c is comprised of a coaxial connector. Connection to thetester 170 is made by way of a cable 171 connected to this contactterminal 50 c. The connection device utilized here is structured asshown in FIG. 2, however the connection device structure is not limitedto the structure of FIG. 2, and needless to say, it may also utilize thestructures shown in FIG. 5, FIG. 6, FIG. 8, FIG. 9 or FIG. 10.

The drive control system 150 is connected to the tester 170 by the cable172. The drive control system 150 sends control signals to each driveactuator of the material support system 160 to control that movement. Inother words, the drive control system 150 is provided with a computerinternally, which controls the operation of the material support system160 according to the test operation progress information for the tester170 sent by way of the cable 172. The drive control system 150 isfurther provided with an operating section 151, to receive inputscontaining all types of instructions relating to drive control such asaccepting instructions for manual operation.

A heater 141 is installed in the support block 162 for performingburn-in testing of the semiconductor device 2. A temperature controller140 regulates the temperature of the semiconductor wafer 1 mounted onthe support block 162 by regulating the cooling jig or the heater 141for the support block 162. A temperature controller system 140 isprovided with an operating section 151, to receive inputs containing alltypes of instructions relating to drive control such as acceptinginstructions for manual operation.

Next, the operation of the test equipment will be described. Thesemiconductor wafer 1 as the item under test is placed on the supportblock 162 and positioned. A plurality of optical image reference marksformed above and separate from the semiconductor wafer 1 (mounted on thesupport block 162) are captured by imaging equipment such as imagesensors or television cameras, and a plurality of position referencemarks are detected from the image signals captured from these images.From the position information obtained from the plurality of referencemarks above the semiconductor wafer 1, two-dimensional positioninformation is calculated for the overall electrode group based on thearray information for semiconductor device 2 arrayed on thesemiconductor wafer 1 as well as array information for the electrodes 3arranged on each semiconductor device 2, obtained from CAD data formodels of semiconductor wafer 1 stored in the drive control system 150or the tester 170. An optical image of designated contact terminal tipsfrom among the plurality of contact terminals 47 formed on themultilayer film 44, or an optical image of a plurality of referencemarks formed separately on the multilayer film 44 is captured by imagingequipment (not shown in drawings) such as a television camera or imagesensor, and the positions of the designated contact terminals or theplurality of reference marks are detected from the image signalsobtained by image capture. The drive control system 150, from positioninformation detected from the plurality of reference marks or designatedcontact terminals on the multilayer film 44, then calculates thetwo-dimensional position information for the overall contact terminalgroup based on probe information such as the array information andheight information, according to the probe model stored by an input fromthe operating section 151. The drive control system 150 then calculatesthe amount of deviation (offset) for two-dimensional positioninformation for the overall electrode group versus two-dimensionalposition information calculated for the overall contact terminal group,and drives the X-Y stage 167 and the swivel mechanism, to position theelectrode 3 group formed on the plurality of individual semiconductordevices arrayed on the semiconductor wafer 1, directly below theplurality of contact terminals 47 group arrayed on the connection device120 a. The drive control system 150 then drives the vertical drivesection 165 for instance, based on the gap with the surface of the area44 a in the multilayer film 44 measured by means of a gap sensor (notshown in drawing) mounted on the support mount 162, and by raising thesupport mount 162 up to a pushed up position 8 to 20 μm from the pointwhere the surface 3 a of the plurality of electrodes (contactedmaterial) 3 are in contact with the tip of the contact terminals, thearea 44 a arrayed with the plurality of contact terminals 47 on themultilayer 44 is made to project and each of the tips of the pluralityof contact terminals 47 is maintained at a highly precise degree oflevelness as shown in FIG. 3 or in FIG. 7 so that the compliancemechanism, along with making the plurality of contact terminals 47follow up on and be parallel with the surface 3 a of the plurality ofelectrodes 3 arrayed on each target semiconductor device, which makesvariations greater than ±2 μm in the height of the individual points ofthe contact terminals be absorbed by localized warping of the cushioninglayer 46, and causes a uniform, low load, contact (about 3 to 50 mN perpin) to be achieved with the electrode (material) 3 arrayed on thesemiconductor wafer 1 connected to the contact terminals 47 at a lowresistance of 0.01Ω to 0.1Ω.

In the drive control system 150, the X-Y stage 167 and swivel mechanismand the vertical drive section 165 are driven and controlled in responseto operating instructions from the operating section 151. The supportmount 162 in particular, is driven upwards by the vertical drive section165 to a pushed up state 8 to 100 μm from the point where the surface 3a of the plurality of electrodes (contacted material) 3 are in contactwith the tip of the contact terminals, and along with the plurality ofcontact terminals 47 following up on and becoming parallel with thesurface 3 a of the plurality of electrodes 3 arrayed on each targetsemiconductor device, variations in the height of the individual pointsof the contact terminals are absorbed by localized warping of thecushioning layer 46, and satisfactory uniform, low load, contact (about3 to 50 mN per pin) is achieved at a low resistance connection of 0.01Ωto 0.1Ω between the plurality of contact terminals 47 and each of theelectrodes 3.

When performing burn-in tests of the semiconductor device 2 while inthis state, temperature regulation of the semiconductor wafer 1 mountedon the support mount 162 is implemented by the heater 141 or cooling jigof the temperature control system 140.

Functions such as the exchange of operation test signals and motoroperation between the tester 170 and semiconductor devices formed on thesemiconductor wafer 1 are implemented by way of the cable 171, thecircuit board 50, the multilayer film 44 and the contact terminals 47and determinations such as pass-fail checks of operating characteristicsof the applicable semiconductor device are performed. In the multilayerfilm 44 at this time, as shown in FIG. 4, a ground layer 49 is installedto enclose the insulation film 66 (74) for the lead out wiring 48connected to each of the terminals 47, and by setting the impedance ZOof the lead out wiring 48 to approximately 40Ω and matching with theimpedance of the tester circuit, distortion and attenuation of theelectrical signals transmitted through the lead out wiring 48 can beprevented, and high frequency electrical signals (high frequencies fromabout 100 MHz up to some 10 GHz) can be utilized with the tester on thesemiconductor device under test to measure device electricalcharacteristics.

Still further, the series of test operations described above can beimplemented on each of the plurality of semiconductor devices formed onthe semiconductor wafer 1 and determinations such as pass-fail checks ofsemiconductor device operating characteristics can be made.

This invention as described above, provides the effect that stable, lowload probing of many pins at a narrow pitch on a semiconductor devicewith a high electrode density can be performed without damage to thedevice under test and furthermore a high speed exchange of electricalsignals or in other words high frequency electrical signals (highfrequencies from about 100 MHz up to some 10 GHz) can be achieved.

This invention provides the further effect that the compliance mechanismachieves a parallel array of pointed contact terminals without slack inthe applicable area of the multilayer film so the pointed contactterminal group makes stable contact with the electrode group of thedevice under test, with only a downward pressure applying a low load oneach pin (approximately 3 to 50 mN) to achieve a stable connection witha low resistance of about 0.05 to 0.1Ω and without generating debrisfrom the electrode material, etc. This invention provides a yet furthereffect that, one or a plurality of semiconductor devices from among aplurality of semiconductor devices (chips) arrayed on a wafer cansimultaneously be stably and reliably contacted at a small contactpressure (about 3 to 50 mN per pin) on the oxidized surface of theelectrodes, formed for instance of aluminum or solder with a stable andlow resistance value of 0.05 to 0.1Ω, and operational tests of eachsemiconductor device can be performed by the tester. In other words, theabove structure of this invention is compatible with devices having ahigh electrode density as well as narrow pitch, and further it canperform testing by simultaneous probing of many discrete chips and canalso perform operational tests with high speed electrical signals (highfrequencies from about 100 MHz up to some 10 GHz). This inventionprovides still another effect in being capable of performing deviceoperating tests at high temperatures, such as burn-in tests, byutilizing material resistant to high temperatures such as polyimide film(insulator film).

This invention provides yet another effect in that a plurality ofcontact terminals with pointed tips can be easily arrayed on themultilayer film by connecting the contact terminals with pointed tips tothe lead out wiring by means of conductive anisotropic sheets ormetallic joints.

1. A method of producing a semiconductor device, comprising the steps of: forming a plurality of semiconductor devices on a wafer; contacting a plurality of contact terminals to electrodes of said semiconductor devices and testing electrical characteristics of said semiconductor devices; and detaching said semiconductor devices from said wafer, wherein said step of testing electrical characteristics of said semiconductor devices includes a step of exchanging an electrical signal between said semiconductor devices and a tester circuit through said contact terminals and wires, wherein the contact terminals are formed by using a wafer with an etched hole as a mold and are made of conductive materials, wherein said wires and said contact terminals are formed separately and both are electrically connected to form a conductive member, wherein said conductive member has an insulation layer, wherein said wires are formed on said insulation layer, and wherein a ground layer is formed on a reverse side of said wires formed on said insulation layer.
 2. A method of producing a semiconductor device according to claim 1, wherein said wires are installed between said ground layer and said contact terminals.
 3. A method of producing a semiconductor device according to claim 1, wherein said wires and said contact terminals are electrically connected by a conductive anisotropic sheet or solder or heat expansion of metal.
 4. A method of producing a semiconductor device according to claim 1, wherein said semiconductor devices are tested in one batch.
 5. A method of producing a semiconductor device according to claim 1, wherein said wires set an impedance by using said ground layer before being electrically connected to said contact terminals.
 6. A method of producing a semiconductor device according to claim 1, wherein said wires set an impedance for matching with said tester circuit.
 7. A method of producing a semiconductor device according to claim 1, wherein said semiconductor device is tested by exchanging high frequency electrical signals higher than 100 MHz through said wires in which impedance is matched with said tester circuit, and wherein said contact terminals have a length equal to or less than 0.5 mm and equal to or more than 0.05 mm.
 8. A method of producing a semiconductor device according to claim 1, wherein said etched hole of said wafer is formed by anisotropic etching. 